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3-Dimensional VLSI: A 2.5-Dimensional Integration Scheme by Prof. Yangdong Deng, Prof. Wojciech P. Maly (auth.)

By Prof. Yangdong Deng, Prof. Wojciech P. Maly (auth.)

"3-Dimensional VLSI: A 2.5-Dimensional Integration Scheme"elaborates the idea that and value of third-dimensional (3-D) VLSI. The authors have constructed a brand new 3-D IC integration paradigm, so-called 2.5-D integration, to handle many difficulties which are tough to solve utilizing conventional non-monolithic integration schemes. The ebook additionally introduces significant 3-D VLSI layout concerns that must be solved via IC designers and digital layout Automation (EDA) builders. by way of treating 3-D integration in an built-in framework, the publication presents vital insights for semiconductor strategy engineers, IC designers, and people operating in EDA R&D.

Dr. Yangdong Deng is an affiliate professor on the Institute of Microelectronics, Tsinghua college, China. Dr. Wojciech P. Maly is the U. A. and Helen Whitaker Professor on the division of electric and machine Engineering, Carnegie Mellon collage, USA.

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Int’l Electronic Device Meeting, 2000, pp. 165  168. [29] M. Koyanagi, H. Kurino, Kang Wook Lee, K. Sakuma, N. Miyakawa, H. Itani. Future system-on-silicon LSI chips. IEEE Micro, Vol. 18, July-Aug. 1998, pp. 17  22. 18 1 Introduction [30] S. Strickland, E. Ergin, D. R. Kaeli, P. Zavracky. VLSI design in the 3rd dimension. Integration: the VLSI Journal, Vol. 25/1, Sep. 1998, pp. 1  16. [31] S. M. Alam, D. E. Troxel, C. V. Thompson. A comprehensive layout methodology and layout-specific circuit analyses for three-dimensional integrated circuits.

5-Dimensional Integration Scheme improving deep-submicrometer interconnect performance and systems-on-chip integration. Proceedings of the IEEE, Vol. 89, 2001, pp. 602  633. [21] V. Subramanian, M. Toita, N. R. Ibrahim, S. J. Souri, K. C. Saraswat. Low-leakage Germanium-seeded laterally-crystallized single-grain 100 nm TFTs for vertical integration applications. , Vol. 20, Jul. 1999, pp. 341  343. [22] G. W. Neudeck, S. Pae, J. P. Denton, T. Su. Multiple layers of silicon-on-insulator for nanostructure devices.

Strickland, E. Ergin, D. R. Kaeli, P. Zavracky. VLSI design in the 3rd dimension. Integration: the VLSI Journal, Vol. 25(1), Sep. 1998, pp. 1  16. [20] S. M. Alam, D. E. Troxel, C. V. Thompson. A comprehensive layout methodology and layout-specific circuit analyses for three-dimensional integrated circuits. In: Proc. Int’l Sym’m on Quality Electronic Design, 2002, pp. 246  251. [21] J. -Q Lu, et al.. A wafer-scale 3-D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects.

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